About this opportunity
NVIDIA Gruppe lists this Senior Physical Design and Timing Engineer opportunity in santa clara, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
We are now looking for a motivated Senior Physical Design and Timing Engineer to join our dynamic and growing team.
What you'll be doing:
Drive physical design and timing of high-frequency and low-power NVIDIA CPUs, GPUs, LPUs and SoCs at block level, cluster level, and/or full chip level.
Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.
Work in a cross-functional environment interacting with multiple teams.
Apply knowledge and experience to improve the convergence flows working with the Methodology Team.
What we need to see:
BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years experience or MS (or equivalent experience) with 3+ years experience in Synthesis and Timing
Solid experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.
Experience in critical path planning and crafting needed.
Hands‑on experience in logic synthesis and equivalence checking/FV. Good understanding of hardware architecture and hands‑on skills in RTL/logic design for timing closure.
Expertise in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power, along with a background in implementing them through ECOs.
Understanding of DFT logic and hands‑on experience in design closure.
Expertise in analyzing and converging crosstalk delay, noise glitch, and electrical/manufacturing rules in deep‑sub micron processes.
Knowledge in process variation effect modeling and experience in design convergence taking into account variations.
Expertise and in‑depth knowledge of industry standard EDA tools.
Proficiency in programming and scripting languages, such as, Perl, Tcl, Make, Python, etc.
Ways to stand out from the crowd:
Background in high‑performance design, such as CPU, GPU, LPU, implementation and timing convergence, this is a plus
Experience with DFT timing closure for various modes e.g. scan shift and capture, transition faults, BIST, etc.
Experience in methodology and/or flow development/automation.
Benefits
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4. You will also be eligible for equity and benefits.
Equal Opportunity Statement
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
#J-18808-Ljbffr
Worksite address
santa clara, CA, 95053, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.