About this opportunity
NVIDIA Corporation lists this Senior Physical Design Engineer opportunity in austin, Texas. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Senior Physical Design Engineer page is loaded## Senior Physical Design Engineerlocations: US, CA, Santa Clara: US, TX, Austintime type: Full timeposted on: Posted Todayjob requisition id: JR We are now looking for a Senior Physical Design Engineer. NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice to join our diverse team today.**What you'll be doing:*** Responsible for all aspects of physical design and implementation of GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets.* As a member of a team, we will all participate in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure.* Craft designs for static timing analysis, power and noise analysis and back-end verification.**What we need to see:*** BSEE (MSEE preferred) or equivalent experience.* 8+ years of experience in large VLSI physical design implementation on 5nm, 4nm and 3nm technology.* Your successful track record of delivering designs to production is a requirement.* Shown experience in the following areas: Power, Performance and Area improvement Initiatives is a plus.* Already a validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD tools from Synopsys (ICC2/DC/PT/STAR-RC/ICV),Cadence (Innovus, Tempus, SeaHawk ) and Mentor Graphics.* Deep understanding of custom macro blocks such as RAMs, CAMs, high-speed IO drivers, PLLs.* Confirmed prior experience in timing closure, clock/power distribution and analysis, RC extraction and correlation, place/ route and tapeout solutions.* To be successful you should possess strong analytical and debugging skills required.* Proficiency using Python, Perl, Tcl, Make scripting is helpful.NVIDIA is widely considered to be the leader of AI computing, and one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you.Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.You will also be eligible for equity and .Applications for this job will be accepted at least until January 31, 2026.This posting is for an existing vacancy.NVIDIA uses AI tools in its recruiting processes.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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Worksite address
austin, TX, 78716, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.