About this opportunity
Altera Corporation lists this Senior Physical Design Engineer — FPGA & SoC Innovation opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Altera Corporation in San Jose, CA, invites a Senior Physical Design Engineer to lead physical implementation of IP and SoC designs from RTL to GDSII, driving timing closure, power optimization, and signoff for next-generation FPGA products.
You will collaborate with RTL, DFT, timing, and CAD teams to deliver high-quality silicon, apply advanced PPA techniques, and continuously improve design flows and automation.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.