About this opportunity
The Consensus lists this Senior Physical Design Engineer - Frontier AI Chips opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Etched is building a new category of AI hardware; as the top-level PD engineer you will own full-chip implementation from floorplanning to GDSII, driving PPA optimization and timing closure. You will collaborate with RTL designers to iterate rapidly and ensure successful tapeouts.
Lead clocking across all corners, manage top-level timing closure, and own PV at block and full-chip levels. Strong Cadence/Synopsys flows and scripting proficiency are essential for success in our fast-paced,
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.