About this opportunity
Celero Communications, Inc. lists this Senior Physical Design Engineer – SoC Tapeout & P&R opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Celero Communications, Inc. is a fast-growing semiconductor startup developing high-performance coherent DSP technology for next-generation AI infrastructure.
We seek an experienced Physical Design Engineer to lead the transformation of complex circuit designs into manufacturable silicon, driving floorplanning, power planning, CTS, timing closure, and physical verification. You will mentor engineers and help define PD methodologies to enable successful tape-out of future chips.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.