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Job description
TSMC Technology Inc. seeks a seasoned Physical Design Verification Lead to drive end‑to‑end verification for CPU blocks toward production tapeouts on N7 or below tech nodes. You will partner with the STA team and lead ECOs for tight timing closure, while addressing EM/Noise and Power/IR challenges.
You will supervise CTS and P&R strategies, optimize block floorplans, and mentor junior engineers, delivering silicon‑quality results at a customer site in the South Bay area.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.