About this opportunity
Celero Communications, Inc. lists this Senior PLL Design Architect for High-Speed Transceivers opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Celero Communications, Inc. seeks a Principal PLL Design Engineer to lead high-speed clocking circuit development for next-generation optical transceivers and SerDes. You will architect and implement PLLs, analyze phase noise, and guide tape-out efforts.
You should have a Master’s or PhD in EE with 5+ years in PLL design, experience with 16nm–2nm nodes, Cadence Virtuoso, EMX/HFSS, and MATLAB. Excellent communication is essential, with a track record of production-level designs.
#J-18808-Ljbffr
Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.