Senior PLL Design Engineer — RF/SerDes Clock Innovation

Job description

Samsung Semiconductor Inc. in San Jose, CA is seeking a Senior/Staff PLL Designer to create PLLs and clock-generation blocks for RF/SerDes. You’ll model, simulate, and verify performance across process corners, collaborating with digital, layout, and systems teams.

A strong background in LM, noise analysis, and RTL calibration is required. Applicants should have 5+ years of PLL experience with deep sub-micron CMOS and proficiency in Verilog/SystemVerilog, Matlab/Simulink, and IC CAD tools.

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Worksite address

san jose, CA, 95199, US

Who can apply

Review the original listing for work authorization, qualifications and employer requirements.