About this opportunity
Hewlett Packard Enterprise Development LP lists this Senior Principal ASIC Design Lead — Networking opportunity in roseville, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Hewlett Packard Enterprise Development LP is seeking a Senior Principal ASIC Design Engineer to lead high‑performance networking ASIC subsystems from architecture through tape‑out. Based in California, you will collaborate with cross‑functional teams to meet power, area, and timing targets while driving design methodology innovations.
The role emphasizes technical leadership, deep Verilog/SystemVerilog expertise, and experience with cutting‑edge AI-augmented design practices.
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Worksite address
roseville, CA, 95678, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.