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Job description
Celero Communication Inc. is seeking a Principal/Senior High-Speed Analog Layout Engineer to drive layout for ADCs, DACs, PLLs and other high-performance blocks.
You will lead cross-functional layout efforts, mentor engineers across time zones, and ensure first-pass silicon success through rigorous checks. This hands-on role requires strong Cadence/Calibre experience, deep device physics understanding, and proven leadership in complex IP layout at FinFET nodes.
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Worksite address
irvine, CA, 92618, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.