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Job description
Cadence Design Systems is hiring a Sr Principal SI/PI Engineer to join the HPP IP R&D Group. You will lead hands-on SI/PI design, testing, and model extraction for high-speed IP products, working closely with chip designers and customers to optimize performance.
The role requires a strong background in SerDes, PCB/FCBGA design, and IBIS-AMI simulations, with excellent communication skills to interact with internal teams and external customers.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.