This job is closed
Applications are no longer available for this announcement. Explore current related opportunities below.
Job description
Credo is seeking a PHY RTL Design Engineer to join our mission to transform connectivity at scale. In this role, you will own RTL architecture, design, implementation, and verification of advanced SerDes DSP blocks used in networking, AI, data center, and HPC products.
This position is onsite at our San Jose HQ. The ideal candidate has strong digital design fundamentals, hands-on RTL development experience, and a solid understanding of high‑speed SerDes.
#J-18808-Ljbffr
Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.