Senior RTL Design Engineer — Space ASICs for Starlink

Job description

SpaceX in Redmond, WA is seeking a Sr. RTL Design Engineer (Silicon Engineering) to develop next-generation ASICs for Starlink deployment.

You will work with cross‑disciplinary teams to design, verify, and optimize RTL in Verilog/SystemVerilog, delivering timing‑accurate, synthesis‑clean designs for space and ground infrastructures. The role requires 5+ years of RTL implementation experience, a bachelor’s degree in engineering or CS, and strong HDL tool proficiency.

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Worksite address

redmond, WA, 98052, US

Who can apply

Review the original listing for work authorization, qualifications and employer requirements.