About this opportunity
Cadence Design Systems lists this Senior RTL/Logic Simulation Architect opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Cadence Design Systems in California is seeking a Senior Engineer for the System Verification Group to advance the Xcelium RTL/logic simulator and tackle the growing complexity of AI and hyperscale chip designs.
You will join a geographically distributed team, lead junior engineers, and contribute to timing analysis and graph algorithms; strong C++ and SystemVerilog skills are essential, with deep expertise in RTL/logic simulation.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.