About this opportunity
Cadence Design Systems lists this Senior RTL/Logic Simulator Architect (C/C++) opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Cadence Design Systems in California is seeking a Senior Engineer for the Xcelium Software Development Team to advance RTL/logic simulation for future AI and hyperscale chip designs. The role is based in California with a distributed global team focused on high‑quality RTL/logic simulation.
Responsibilities include enhancing the Xcelium engine, optimizing performance in C/C++, implementing graph algorithms for SDC constraints, and writing specifications and unit tests.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.