Senior Silicon Timing & Design Engineering Lead

Job description

Intel Corporation in Santa Clara is seeking a Physical Design Timing Engineer to ensure optimal timing, power efficiency, and performance of SoC designs. You will collaborate with cross-functional teams to develop advanced methodologies and drive timing solutions across chip blocks.

The role requires extensive experience in timing analysis, constraint generation, and clocking flows, with proficiency in TCL scripting, and a strong foundation in digital design and power-performance optimization.

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Worksite address

santa clara, CA, 95053, US

Who can apply

Review the original listing for work authorization, qualifications and employer requirements.