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Job description
AMD in San Jose, CA is seeking an adaptive design verification engineer to join our SOC team. You will develop and maintain tests to drive functional and performance verification for core and SOC level, collaborating across sites.
The role emphasizes strong coding in Verilog/SystemVerilog, UVM, C/C++, and scripting (Perl/Python). You will contribute to testbench components and help close coverage metrics while enabling next-generation IP delivery.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.