About this opportunity
Xcelerium lists this Senior SoC PD Engineer – Lead Tapeout & PPA opportunity in irvine, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
A semiconductor company is seeking a Senior SoC/ASIC Physical Design Engineer who will lead the physical design activities and collaborate closely with engineering teams. This role involves establishing modern design flows and optimizing performance while focusing on design closure, employing cutting-edge technologies in developing edge processors. Candidates with over 10 years of experience in ASIC/SoC design and strong expertise in Synopsys EDA tools are preferred. An excellent compensation package is offered.
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Worksite address
irvine, CA, 92713, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.