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Job description
Velaura AI, Inc. is seeking an experienced Design Verification Engineer focusing on system-level verification for its Physical AI SoC. You will verify boot flows, security state transitions, and IO/memory subsystems across typical workloads.
The role requires leadership in verification projects and hands-on experience with CDC/RDC tools, low power flows, and emulation or FPGA prototyping to accelerate tape-out readiness.
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Worksite address
santa clara, CA, 95053, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.