About this opportunity
Altera Corporation lists this Senior Timing Methodology Lead for FPGA/ASIC opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Altera, located in San Jose, CA, seeks a senior Design Automation engineer focused on Static Timing Analysis and timing modeling for ASIC/IP/FPGA timing flows. You will lead a small team, own production‑grade flows, and drive cross‑functional engagements with design teams and external vendors.
The role emphasizes greenfield characterization, mentoring engineers, and delivering timing sign-off in a unified flow, with AI/ML-infused automation and strong Python/Tcl scripting background required.
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Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.