About this opportunity
TSMC - Taiwan Semiconductor Manufacturing Company Limited lists this Senior VLSI Engineer - DRC/LVS, Clocking & ECOs opportunity in california, Missouri. Review the employer’s description below for duties, qualifications and application requirements.
Job description
TSMC North America in San Jose, CA seeks a Senior Engineer to own design rule checks, LVS/ERC/antenna cleanup, floorplan analysis and congestion resolution. You will fix power integrity and EM issues, perform signal EM/noise analysis, and sign off on physical verification for complex blocks.
The role requires a Master’s degree in Electrical or Computer Engineering and at least one year of related experience, with hands-on knowledge of VLSI design, digital ICs, design-for-testing, computer
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Worksite address
california, MO, 65018, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.