About this opportunity
Semiconductor Engineering lists this SerDes IP Systems Engineering Director Cadence opportunity in san jose, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
This is a unique opportunityto join the rapidly growingDie-to-Die Interface IP team in the Silicon Solutions R&D Group at Cadence Design Systems. We are looking for a Systems Engineering Directorwho will bea key driver and contributor to the development of ouradvanced D2D SerDes IP products.This role involves leading the D2D Systems analysis team as well as contributing withhands ontechnical development.
#J-18808-Ljbffr
Worksite address
san jose, CA, 95199, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.