About this opportunity
Apple Inc. lists this SoC Physical Design & Timing Engineer opportunity in beaverton, Oregon. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Apple Inc. in Beaverton, Oregon is seeking a skilled physical design engineer to drive partition-level implementation for a complex SOC. You will collaborate with the logic team from early architecture through netlist to GDS2, ensuring timely delivery and signoff.
The role requires sub-10nm experience, large SOC work, and robust proficiency with standard EDA tools to meet aggressive die-size and performance goals.
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Worksite address
beaverton, OR, 97078, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.