About this opportunity
Anysilicon lists this Sr. ASIC Design Engineer opportunity in roseville, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Job Description:
Hewlett Packard Enterprise (HPE) is seeking a Senior ASIC Design Engineer to join its Networking Silicon group, focusing on the development of advanced networking chips for routers and switches. This role is primarily onsite at an HPE office, emphasizing collaboration and innovation in a fast-paced environment. HPE values diverse backgrounds and offers a culture that supports personal and professional growth.
Responsibilities:
Develop detailed micro-architecture specifications from functional specifications that meet power and area requirements.
Write functional coverage and SystemVerilog Assertions (SVA) to assist in verification and catch corner case bugs.
Collaborate with the Physical Design team for optimal floorplan and timing closure, identifying and fixing timing issues in RTL to meet frequency targets.
Work with the Verification team to ensure full validation of design blocks.
Mentor and provide guidance to new engineers and interns.
Qualifications:
Bachelor’s degree in Electrical Engineering (Master’s preferred) with 5+ years of relevant experience.
Strong analytical and problem-solving skills.
Knowledge of computer architecture and networking protocols is a plus.
Proficient coding skills in Verilog/System Verilog from coursework or prior experience.
Familiarity with synthesis, lint, and other EDA tools is desired.
Excellent written and verbal communication skills.
Skills:
Proficiency in Verilog/System Verilog.
Knowledge of Perl/Python is a plus.
Experience with AI agentic tools is a plus.
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Worksite address
roseville, CA, 95678, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.