About this opportunity
WarmStart Ltd lists this Sr. ASIC Design Engineer [Silicon Engineering] opportunity in irvine, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
SpaceX is seeking a motivated and proactive Senior ASIC Design Engineer to join its Silicon Engineering team. This role involves developing next-generation ASICs for deployment in space and ground infrastructures, contributing to the Starlink project, which aims to provide fast and reliable internet globally. The ideal candidate will work with cross-disciplinary teams to enhance the performance and capabilities of the Starlink network.
Responsibilities
Evaluate architectural trade-offs based on features, performance requirements, and system limitations.
Define micro-architecture, implement RTL in Verilog/System Verilog, and deliver fully verified, synthesis/timing clean designs.
Collaborate with the verification team to ensure comprehensive design coverage and verification.
Provide timing constraints for IPs and support the physical implementation team in synthesis and timing closure.
Participate in silicon bring-up and validation.
Qualifications
Bachelor's degree in electrical engineering, computer engineering, or computer science.
5+ years of experience in RTL implementation.
Skills
Problem-solving skills, particularly in clock domain crossings and power optimization.
Experience in ASIC/SoC system integration and embedded CPU subsystems.
Familiarity with standard bus protocols (e.g., AXI, AHB).
Knowledge of high-speed and low-power design techniques.
Experience with EDA tools such as HDL simulators and HDL Lint tools.
Team-player with a can-do attitude, capable of working well in a group while contributing individually.
Eagerness to learn new skills and tackle challenges.
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Worksite address
irvine, CA, 92713, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.