About this opportunity
Advanced Micro Devices lists this SR Design Verification Engineer opportunity in santa clara, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE
AMD’s Network Technologies Solutions Group (NTSG) is a leading provider of advanced data center networking technology. Our distributed services platform expands AMD’s data center product portfolio with a high‑performance DPU and software stack deployed at scale across major cloud and enterprise environments, including Goldman Sachs, IBM Cloud, Microsoft Azure, and Oracle.
THE PERSON
We are seeking a high‑impact Design Verification Engineer with strong technical depth, ownership, and the ability to drive verification closure on complex, high‑performance ASIC designs. The ideal candidate brings hands‑on verification expertise, excels in debugging intricate architecture/RTL issues, and is comfortable leading verification efforts across IP, subsystem, and SoC levels.
You will work in a fast‑paced, highly collaborative environment and contribute directly to the success of next‑generation AMD networking products.
KEY RESPONSIBILITIES
Verification Architecture & Testbench Development Develop robust UVM‑based testbench architectures for IP, subsystem, and SoC‑level verification.
Drive test plan creation, feature mapping, and coverage strategy for complex networking and data‑path IP.
Develop high‑quality SystemVerilog components: stimulus generators, agents, BFMs/transactors, scoreboards, checkers, assertions, and functional coverage models.
Execution, Debug & Closure Own execution of verification plans, regression triage, and debug of architectural, functional, and performance issues.
Root‑cause complex failures across RTL, testbench, interfaces (PCIe/DDR/Ethernet), and system interactions.
Optimize simulations, coverage closure, and verification sign‑off methodology.
Tools & Methodology Use industry‑standard simulation, debug, and analysis tools (VCS, Verdi/DVE, coverage tools, waveform analysis suites).
Contribute to verification methodology improvements, automation, and infrastructure enhancements (Python/Tcl/Make).
Cross‑Functional Collaboration Collaborate closely with RTL design, architecture, validation, firmware, and emulation/HAPS teams to ensure high‑quality deliverables.
Participate in design reviews, micro‑architecture definition, and bring a verification perspective into early design stages.
Mentor junior engineers and provide technical leadership within the verification team.
LANGUAGES & TOOLS
Required Expert‑level knowledge of SystemVerilog and UVM
Strong hands‑on experience with SystemVerilog simulators (VCS preferred) and waveform debuggers (Verdi/DVE)
Proven experience in verifying complex IP/subsystems with test plans, coverage, and constrained‑random methodologies
Strong debug skills across architecture, RTL, and testbench layers
Experience with industry protocols such as PCIe, AXI, Ethernet, DDR, DMA engines, or similar data‑path components
Scripting skills in Python, Perl, Shell, Tcl, or equivalent for automation and infrastructure
Preferred Experience with performance verification, power‑aware verification (UPF), or formal verification
Familiarity with FPGA/HAPS‑based validation and acceleration flows
Understanding of networking or high‑speed I/O pipelines
Exposure to architectural modeling or C/C++ reference models
PREFERRED QUALIFICATIONS
Strong analytical and problem‑solving abilities with a proven track record of debugging complex issues
Ability to lead verification tasks independently and drive cross‑team closure
Excellent verbal and written communication skills
Comfortable working in a fast‑paced, collaborative, multi‑site environment
Ability to mentor and guide junior DV engineers
ACADEMIC CREDENTIALS
Bachelor’s Degree in Electrical/Computer Engineering or related field, Master’s Preferred.
LOCATION
Santa Clara, CA
This role is not eligible for visa sponsorship.
EEO STATEMENT
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee‑based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
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Worksite address
santa clara, CA, 95053, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.