About this opportunity
SiFive, Inc. lists this Staff CPU RTL Design Engineer - RISC-V Core & MMU opportunity in santa clara, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
SiFive, Inc. is seeking a Staff RTL Design Engineer to join their team in Santa Clara, California. You will work on designing CPU cores based on RISC-V architecture, contributing to cutting-edge hardware developments.
The ideal candidate should have a BS/MS in engineering, at least 3 years of design experience, and proficiency in RTL design languages like Verilog or System Verilog. SiFive offers competitive pay, incentives, and a comprehensive benefits package.
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Worksite address
santa clara, CA, 95053, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.