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Job description
Powerlattice Technologies Inc. is seeking a Senior or Staff Digital Design Engineer to own digital blocks and RTL development for SoCs.
The role collaborates with verification, DFT, physical implementation, firmware, and systems teams in a startup environment where individual contributions drive product success. The candidate will design microarchitecture, code synthesizable RTL, and assist with timing closures, LEC, and post-silicon debugging as part of a hybrid work model at Chandler, AZ or
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Worksite address
chandler, AZ, 85249, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.