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Job description
ASIC DFT Engineer II Full Time – United States
Cisco's Silicon One team is seeking potential candidates for the role of ASIC Design for Test Engineer, focusing on Design-for-Test (DFT) within innovative hardware platforms that drive core Switching, Routing, and Wireless products. This role emphasizes collaboration and creativity in a global team environment, contributing to the future of technology in the AI era.
Responsibilities:
Implement Hardware Design-for-Test (DFT) features for ATE, in-system test, debug, and diagnostics.
Create and enhance automation scripts for improved implementation efficiency.
Collaborate with Design, Design Verification, and Physical Design teams for test logic integration and validation.
Validate test timing and logic equivalency using SystemVerilog.
Utilize ATPG and EDA tools for test pattern generation and analysis.
Qualifications:
Master's degree with 0 years of experience or Bachelor's degree with 2 years of experience in ASIC Engineering or related field.
Foundational understanding of JTAG protocols, scan architectures, and Built-In Self-Test (BIST).
Familiarity with EDA and ATPG tools, and scripting skills in Python, Tcl, or Perl.
Experience with gate-level simulations and debugging using simulators like VCS.
Skills:
Practical experience in verification skills, including SystemVerilog and logic equivalency checking.
Understanding of VLSI circuit behaviors and basic timing concepts.
Exposure to post-silicon validation using DFT patterns and Test Static Timing Analysis.
Strong verbal and written communication skills for effective collaboration.
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ASIC Design Services
Verification
Packaging & Wafer
Semiconductor IP
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Tell us what you're building and we'll recommend qualified vendors for your project.
ASIC Design Services
Verification
Packaging & Wafer
Semiconductor IP
Work Email
Free No obligation Response within 24 hours
#J-18808-Ljbffr
Worksite address
san jose, CA, 95199, US
Who can apply
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