About this opportunity
SiFive lists this Lead Design Verification Architect – Cache-Coherent Interconnect opportunity in santa clara, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
SiFive, a leader in RISC-V-based compute, seeks a Principal Design Verification Engineer to steer verification for a cache-coherent interconnect subsystem used in high-performance CPU/SoC platforms.
You will partner with architecture, RTL, formal, and performance teams to ensure protocol correctness, ordering, flow control, and robust integration across interfaces while mentoring engineers and advancing reusable DV infrastructure.
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Worksite address
santa clara, CA, 95053, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.