About this opportunity
Qualcomm lists this Next-Gen, High-Speed HBM, LPDDR Memory Subsystem ASIC Digital Design Engineer opportunity in san diego, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Company
Qualcomm Technologies, Inc.
Job Area
Engineering Group, Engineering Group > ASICS Engineering
General Summary
Next Generation, High-Speed, Memory and Cache Controller and Advanced Memory NoCs based Subsystem Design Team is looking for Senior ASIC Design Engineers for the next generation high-speed HBM/LPDDR/DDR memory subsystems. The front end of the DDR controller interfaces to the rest of the system such as CPU, GPU, DSP, and Multimedia Processors, and the engineer is expected to enable high-speed (1GHz+) designs in QCT products. The candidate will work on architecture, design (RTL coding), and deployment of the next-generation high-speed memory subsystems into QCT products, develop architecture and design specifications, drive micro-architecture of portions of the logic design, implement and deliver RTL, and work with verification engineers to deliver high-quality designs. Responsibilities include debugging designs, providing debug support during chip integration, synthesis, timing closure, physical design support, gate-level simulations, and power analysis, and making regular contributions to improve design methodology, productivity, and quality of results.
Qualifications
Bachelor's or Master’s degree in Science, Engineering, or related field.
5+ years ASIC design, RTL coding, and front-end digital design experience.
3+ years Hardware Architecture experience.
Preferred Qualifications
3–10 years of ASIC design (RTL coding).
Exposure to RTL Design Verification flows.
3+ years of direct Hardware Architecture experience.
Bachelor’s degree in Electrical or Computer Engineering with at least 5+ years of high-speed digital design experience (Master’s degree preferred).
Experience with LPDDR memory and cache controller, NoC-based architectures interfacing to CPUs, DSPs, and multimedia processors.
Exposure to HBM memory type designs.
On-chip tightly coupled SRAM & L3 cache controller architecture/design.
Experience with x86 or ARM CPU/bus architectures.
Ordering of memory transactions and methods to enforce proper ordering to conform to ISA architecture specifications.
Education Requirements
Required: Bachelor’s, Computer Engineering and/or Electrical Engineering. Preferred: Master’s, Computer Engineering and/or Electrical Engineering.
Minimum Qualifications
Bachelor’s degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
Master’s degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
Pay range and Other Compensation & Benefits
Pay range: $140,000.00 – $210,000.00. Additional compensation includes a competitive annual discretionary bonus program and opportunities for annual RSU grants. Extensive benefits package supports success at work, at home, and in play.
EEO Employer
Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.
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Worksite address
san diego, CA, 92189, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.