About this opportunity
Wipro lists this Senior ASIC / SoC Network-on-Chip Design Engineer or Senior ASIC Design Engineer opportunity in san diego, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Wipro Limited (NYSE: WIT, BSE: , NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future‑ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever‑changing world. For additional information, visit us at
Job Description
Job Title: Senior ASIC / SoC Network-on-Chip Design Engineer or Senior ASIC Design Engineer
City: Mountain View
State/Province: California
Posting Start Date: 9/18/26
Responsibilities
Design high-performance, high-bandwidth Network-on-Chip (NoC) IP for advanced AI SoCs.
Define microarchitecture specifications and develop synthesizable RTL using Verilog/SystemVerilog.
Drive synthesis, timing constraints, CDC/Lint closure, and PPA optimization.
Integrate IP across SoC subsystems and support post-silicon debug.
Collaborate with architecture, verification, physical design, and SoC integration teams.
Develop Python scripts for design automation and productivity.
Qualifications
8+ years delivering ASIC/SoC IP designs.
6+ years of hands‑on digital design, RTL, and microarchitecture experience.
Strong experience with Verilog/SystemVerilog, synthesis, timing constraints, CDC, Lint, and PPA trade‑offs.
Experience with NoC/interconnect and high‑throughput/low‑latency designs.
Experience with SoC integration, post‑silicon debug, and Python scripting.
Key Skills: ASIC | NoC | RTL | SystemVerilog | Microarchitecture | CDC | Lint | Synthesis | Timing | PPA | Python Mandatory Skills: VLSI Physical Place and Route.Experience: 3-5 Years.
The expected compensation for this role ranges from $60,000 to $140,000 .
Based on the position, the role is also eligible for Wipro's standard benefits including a full range of medical and dental benefits options, disability insurance, paid time off (inclusive of sick leave), other paid and unpaid leave options.
Wipro provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws. Applications from veterans and people with disabilities are explicitly welcome.
We are an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, caste, creed, religion, gender, marital status, age, ethnic and national origin, gender identity, gender expression, sexual orientation, political orientation, disability status, protected veteran status, or any other characteristic protected by law.
Wipro is committed to creating an accessible, supportive, and inclusive workplace. Reasonable accommodation will be provided to all applicants including persons with disabilities, throughout the recruitment and selection process. Accommodations must be communicated in advance of the application, where possible, and will be reviewed on an individual basis. Wipro provides equal opportunities to all and values diversity.
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Worksite address
san diego, CA, 92189, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.