About this opportunity
Tensordyne lists this Senior ASIC STA Engineer — Timing & Full-Chip Mastery opportunity in workfromhome, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Tensordyne, a Sunnyvale-based AI system solutions company, is seeking a senior ASIC STA lead to drive frontend physical design and timing closure across full-chip and block-level workstreams. You will collaborate with a global team, develop scalable STA workflows, and optimize timing with Cadence/Synopsys tools in a fast-paced HPC environment.
Ideal candidates have 10+ years in ASIC design, strong SDC skills for PCIe/SerDes interfaces, and a track record leading backend teams, while enjoying a
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Worksite address
workfromhome, CA, 94087, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.