About this opportunity
D-Matrix Corp. lists this Sr. Staff PCB Design Engineer opportunity in santa clara, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible.Our culture is one of respect and collaboration.
We value humility and believe in direct communication.We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI.
Role Overview
As Sr. Staff PCB Design Engineer, you will lead the physical design of the boards that connect d-Matrix's AI silicon to the world. Our "Corsair" platforms push the limits of signal density and power delivery, and you will own layout for high-complexity, high-layer-count PCBAs (20+ layers) — ensuring 112G/224G SerDes signals stay clean and thousands of amps are delivered with minimal loss. Beyond hands-on layout, you will serve as custodian of our Design Methodology, driving the automation, tooling, and constraint management processes that let hardware development scale with precision and speed. You'll partner closely with power, ASIC, and manufacturing teams, and have the autonomy to build layout infrastructure from the ground up.
What You Will Do
Lead full-cycle layout for high-complexity AI accelerator cards (PCIe form factors) and system baseboards
Architect and manage the Constraint Manager (CM) hierarchy in Cadence Allegro, defining the source of truth for high-speed routing rules and electrical constraints
Develop automation scripts (SKILL, Python, or TCL) to streamline layout tasks, DRC checks, and reporting
Execute layout for ultra-high-speed interfaces including PCIe Gen5/6, CXL, and custom die-to-die (D2D) interconnects
Partner with Power Engineers on PDN strategy, including multi-phase VRM layouts and decoupling capacitor placement for high-TDP ASICs
Drive PCB stack-up definition, including advanced low-loss materials (e.g., Megtron 7/8) and hybrid build-ups
Serve as primary interface with fabricators and CMs to ensure DFM, DFT, and DFA requirements are met for high-yield production
What You Will Bring
BS in Electrical/Electronic Engineering or equivalent practical experience
10+ years of experience in high-speed, high-density PCB layout for servers, networking, or AI accelerators
Proficiency in Cadence Allegro Constraint Manager, including T-junctions, differential pair phase-tuning, and Z-axis delay matching
Proven ability to write and deploy SKILL scripts or use Allegro's API to automate design audits and layout routines
Deep understanding of high-speed routing techniques (back-drilling, via-in-pad, skip-vias) and HDI/ELIC design
Proven track record routing 112G SerDes and complex DDR5/HBM interfaces
Preferred Qualifications
Experience establishing a Library Management System and standardized footprint/padstack creation processes
Familiarity with PLM/PDM integration for managing layout releases and ECO workflows
Knowledge of PCB warpage mitigation strategies for large-form-factor ASICs and MCMs
Equal Opportunity Employment Policy
d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.
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Worksite address
santa clara, CA, 95053, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.