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Job description
Intel is shaping the future of technology with a focus on reliability design enablement for PDKs and TFMs across leading nodes. The role drives PDK design rule development, quality benchmarks, and collaboration with internal teams and EDA vendors to ensure robust design verification and optimal performance.
The candidate will work in a hybrid model with a strong emphasis on cross-functional communication, risk assessment, and continuous improvement in design reliability for silicon and packaging
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Worksite address
hillsboro, OR, 97104, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.