About this opportunity
Anysilicon lists this Senior Staff Engineer, Digital IC Design opportunity in santa clara, California. Review the employer’s description below for duties, qualifications and application requirements.
Job description
Marvell is a leading provider of semiconductor solutions that form the backbone of data infrastructure across various sectors, including enterprise, cloud, AI, and automotive applications. The company is dedicated to fostering innovation that has a lasting impact on industries and individual lives. The Custom Compute, Storage and Automotive Business Unit focuses on delivering high-performance solutions utilizing advanced technologies such as CXL, PCIe, Ethernet, and ARM CPU cores.
Responsibilities:
Integrate internal and external IP blocks at the chip level with the SOC Integration team.
Take ownership of a portion of SOC design from initial stages to completion.
Collaborate on floorplan and manage interconnection of IP blocks.
Conduct static checks and assist with subsystem and chip-level verification efforts.
Drive to timing closure and collaborate with cross-disciplinary teams to ensure high-quality product tape-out.
Utilize industry and internal EDA tools for functional simulations, gate-level simulations, and code quality checks.
Lead design efforts for internally developed processor IP blocks to meet architectural needs.
Work closely with verification and implementation teams to fulfill product requirements.
Deliver micro-architectural specifications and participate in automation tool development to enhance workflows.
Leverage next-generation AI tools to improve existing processes.
Qualifications:
Bachelor’s degree in Computer Engineering, Electrical Engineering, or related fields with 5+ years of experience, or a Master’s/PhD with 3+ years of experience.
Proven experience in taping out complex SoCs and post-silicon debug.
Strong RTL design skills in SystemVerilog.
Hands-on experience with SoC integration, clock/reset design, CDC, and timing constraints.
Understanding of front-end RTL decisions and their impact on physical implementation and verification.
Familiarity with ARM protocols (APB, AHB, AXI, CHI) and SoC interconnect architectures.
Skills:
Excellent communication and problem-solving skills.
Strong analytical abilities.
Experience with scripting languages such as Python or Tcl.
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Worksite address
santa clara, CA, 95053, US
Who can apply
Review the original listing for work authorization, qualifications and employer requirements.